The three clock frequency ranges are shown in the following table.
Control | QSPIx_CLK Frequency Range | Register Bit Field | ||
---|---|---|---|---|
≤ 37.5 MHz | >37.5 to 100 MHz | >100 to 150 MHz | ||
Data tap delay unit bypass |
Bypass |
Bypass |
Enable |
PMC_IOP_SLCR.IOP_TAPDLY_BYPASS [LQSPI_RX] |
Clock loopback pin enable |
Disable |
Enable |
Enable |
LPBK_DLY_ADJ [USE_LPBK]1 |
Data tap delay settings | 00, 000 | 00, 000 | 01, 000 | LPBK_DLY_ADJ [DLY1], [DLY0] |
Data delay enable | Disable (0) |
Enable |
Disable |
DATA_DLY_ADJ [USE_DATA_DLY] |
Data delay adjustment | 000 | 000 | 000 | DATA_DLY_ADJ [DATA_DLY_ADJ] |
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