The APU and subsystems include support for the Arm server based system architecture (SBSA). The SBSA architecture aligns hardware with system software components for interoperability. The specification comprises multiple levels that build incrementally on top of each other with each level mandating additional functional aspects of the system. This includes specifying features that the CPU and some key peripherals need to support to be compliant.
The Versal adaptive SoC system is Arm SBSA Level-1 capable, at a minimum, as defined by the Arm SBSA specification document number ARM-DEN-0029A.
The features specifically supporting the SBSA architecture include:
- SBSA L1 compatible components
- APU Cortex-A72 core
- UART SBSA
- SWDT with generic and windowed timers
- APU generic interrupt controller (Arm GICv3 architecture
in GIC-500)
- Locality-specific peripheral interrupt (LPI)
- System register interface enable (SRE)
- Affinity routing enable (ARE)
- System firmware data structures such as ACPI or FDT