APU SMID Bits [3:0]

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

APU SMID [3:0] bits are derived from the APU AXI ID. The following table lists the APU SMID bits.

Table 1. APU SMID Bits
AXI_ID[6:5] SMID [3:0]
00 1000
01
10
11 0 | AXI_ID[2:0]