The system watchdog timer block diagram is shown in the following figure.
Figure 1.
System
Watchdog Timer Block Diagram
I/O Signals
The I/O signals coming from the SWDT are shown the SWDT I/O Interface section.
Clock Selection
The following table describes the SWDT CLK selections.
| SWDT Name | Clock Options | Register Control |
|---|---|---|
| LPD_SWDT | Select clock:
|
LPD_IOP_SLCR.SWDT_Clk_Sel |
| FPD_SWDT | Select clock:
|
FPD_SLCR.SWDT_Clk_Sel |
Interrupt and Error Signals
The SWDT interrupt signals are listed in a table in the System Interrupts Table section.
The LPD and FPD SWDT error signals are routed to the PSM error accumulator module. They are listed in the System Errors to PSM EAM table.