The EMIO interface to the PL provides design flexibility for the interface protocol.
| Signal Name | Ref Clock | I/O | Description |
|---|---|---|---|
| Miscellaneous Signals | |||
| GMII_speed_mode[3:0] | – | O | Speed mode |
| Receive Signals | |||
| GMII_rx_clk | – | I |
Receive clock from the system clock generator: • 125 MHz for gigabit GMII operation. • 25 MHz for 100M operation. • 2.5 MHz for 10M operation. |
| GMII_rx_crs | GMII_rx_clk | I | Carrier sense from the PHY. |
| GMII_rx_col | GMII_rx_clk | I | Collision detection from the PHY. |
| GMII_rx_rxd[7:0] | GMII_rx_clk | I |
Receive data from the PHY: • 10/100 mode: rxd[3:0] used, rxd[7:4] not used. • 1000 mode: rxd[7:0] used. |
| GMII_rx_dv | GMII_rx_clk | I | Receive data valid signal from the PHY. |
| GMII_rx_er | GMII_rx_clk | I | Receive error signal from the PHY. |
| Transmit Signals | |||
| GMII_tx_clk | – | I |
Transmit clock from the system clock generator. • 125 MHz for gigabit operation • 25 MHz for 100M operation • 2.5 MHz for 10M operation |
| GMII_txd[7:0] | GMII_tx_clk | O |
Transmit data to the PHY. 10/100 mode: txd[3:0] used, txd[7:4] tied to logic 0. 1000 mode: txd[7:0] used. |
| GMII_tx_en | GMII_tx_clk | O | Transmit enable to the PHY |
| GMII_tx_er | GMII_tx_clk | O | Transmit frame error signal to PHY. Asserted if the DMA block fails to fetch data from memory during frame transmission. |