CTI Summary Table

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The CTI units are summarized in the following table with links to the individual CTI port channel tables and the associated register set.

Table 1. Cross-Trigger Interface Summary Table
Description Register Module Name Register Module Type Notes
FPD CTI Ports
APU Core 0 DBG_APU0_CTI DBG_A720_CTI Integrated in APU core
APU Core 1 DBG_APU1_CTI DBG_A721_CTI Integrated in APU core
Dual APU DBG_APU_CTI DBG_CTI link to Versal Adaptive SoC Register Reference (AM012) CTI 1A
FPD SoC DBG_FPD_SOC_CTI CTI 1B
FPD PS-PL DBG_FPD_PSPL_CTI CTI 1C, PS-PL, and PL-PS
LPD CTI Ports
RPU Core 0 DBG_RPU0_CTI DBG_CTI Integrated in RPU core
RPU Core 1 DBG_RPU1_CTI Integrated in RPU core