System-Level Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The USB controller is included two clock and reset register modules (CRL and CRP). The controller is located in the LPD, but the PHY controller interface is in the PMC.

  • LPD_IOP_SLCR at 0xFF08_0000.
  • PMC_IOP_SLCR at 0xF106_0000