I/O Buffer Pin Banks

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The following table lists the I/O buffer pin banks.

Table 1. PMC, PS, and Other I/O Buffer Pin Banks
Bank Name Pin Count Buffer Type Description
PMC DIO Bank 15 Digital Dedicated I/O with POR_B, REF_CLK, JTAG, and boot mode.
PMC DIO_A Bank 4 Analog

PMC MIO Bank 0
PMC MIO Bank 1

52 Digital

Multiplexed I/O for boot devices and peripherals in the PMC and LPD IOPs. See Multiplexed I/O Signals and Pins and Output Buffer Control Registers.

LPD MIO Bank 26 Digital
PL XPIO 54 per bank XP IOB The XPIO banks are normally used by the DDRMC, but are available for use by the PL except for the XPIO banks located in the corners of the die. The XP I/O interconnect logic (IOL) and I/O block (IOB) resources are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) with the layout described in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
PL HDIO Varies Digital Multiple banks of HDIO buffers connect PL to device pins. The HDIO IOL and IOB resources are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
GTYP 1 16 Transceiver

CPipe GTYP transceivers connect CPM5 PCIe lanes and Aurora debug to I/O pins. PL GTYP transceivers connect the PL to I/O pins.

GTY 1 Varies Transceiver XPipe GTY transceivers connect CPM4 PCIe lanes, Aurora debug, and PL to I/O pins. PL GTY transceivers connect the PL to I/O pins.
GTM Varies Transceiver The GTM transceivers are listed in Versal Architecture and Product Data Sheet: Overview (DS950).
  1. The GTY and GTYP transceivers functionality and specifications are defined in the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).