FPD CTI Ports

APU Core 0 CTI
            DBG_A720_CTI
         register module
APU Core 1 CTI
            DBG_A721_CTI
        

0: Debug trigger, DBGTRIGGER
1: PMU interrupt, PMUIRQ
2: reserved
3: reserved
4: ETM EXTOUT 0
5: ETM EXTOUT 1
6: ETM EXTOUT 2
7: ETM EXTOUT 3

IN port 0
IN port 1
-
-
IN port 4
IN port 5
IN port 6
IN port 7

OUT port 0
OUT port 1
OUT port 2
-
OUT port 4
OUT port 5
OUT port 6
OUT port 7

0: EDBGRQ
1: Debug restart EBGRESTART
2: GIC PPI 24 CTIIRQ
3: reserved
4: ETM ExtIn 0
5: ETM ExtIn 1
6: ETM ExtIn 2
7: ETM ExtIn 3

SW acknowledge
HW handshake
SW acknowledge
-
HW handshake
HW handshake
HW handshake
HW handshake

0 - 1: reserved
2: ETF full
3: ETF ACQCOMP
4 - 7: reserved

-
IN port 2
IN port 3
-

-
OUT port 2
OUT port 3
OUT port 4
OUT port 5
-

0 - 1: reserved
2: ETC FLUSHIN
3: ETF TRIGIN
4: PMUSNAPSHOT0
5: PMUSNAPSHOT1
6 - 7: reserved

-
HW handshake
HW handshake
HW handshake
HW handshake
-

0: STM TRIGOUTSPTE
1: STM TRIGOUTSW
2: STM TRIGOUTHETE
3: STM ASYNCOUT
4: ETF 1 FULL
5: ETF 1 ACQCOMP
6: ETR FULL
7: ETR ACQCOMP

IN port 0
IN port 1
IN port 2
IN port 3
IN port 4
IN port 5
IN port 6
-

OUT port 0
OUT port 1
OUT port 2
OUT port 3
OUT port 4
OUT port 5
OUT port 6
OUT port 7

0: STM HWEVENTS[60, 62_b]¹
1: STM HWEVENTS[61, 63_b]¹
2: TPIU FLUSHIN
3: TPIU TRIGIN
4: ETF 1 FLUSHIN
5: ETF 1 TRIGIN
6: ETR FLUSHIN
7: ETR TRIGIN

0: Probe 0, PL to PS trigger, PL_PS_TRIGx
1: Probe 1
2: Probe 2
3: Probe 3
4 - 7: reserved

IN port 0
IN port 1
IN port 2
IN port 3
-

OUT port 0
OUT port 1
OUT port 2
OUT port 3
-
OUT port 6
OUT port 7

0:  Probe 0, PS to PL trigger, PS_PL_TRIGx
1: Probe 1
2: Probe 2
3: Probe 3
4 - 5: reserved
6: Halt system timer
7: Restart system timer

HW handshake
HW handshake
HW handshake
HW handshake
-
SW acknowledge
HW handshake