Clocks

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

There are many clocks in the device for clocking logic and I/O. This chapter describes the clocks in the PMC and processing system. This includes clock generators, clock dividers for reference clocks, and the various destinations within the device.

PMC and PS Clocks

The clocks associated with the PMC, processing system, and CPM are described in the following sections:

  • The Clock Distribution shows the major internal clocks for the PMC, LPD, and FPD
  • Three root clocks originate in the PMC and are described in PMC Source Clocks section:
    • REF_CLK (reference clock input device pin)
    • PMC_IRO_CLK (PMC internal ring oscillator)
    • RTC (real-time clock)
  • There are five programmable PLL Clock Generators: two in the PMC and one in the LPD, FPD, and CPM
  • Dozens of programmable Reference Clock Frequency Dividers are used to generate clocks for various blocks in the system
Note: Most devices require a single REF_CLK. Some stacked silicon interconnect (SSI) technology devices require multiple reference clocks. For additional information, see the SSI Multiple Super Logic Regions section.

CPM Clocks

The clocks for the CPM are described in the Versal Adaptive SoC CPM CCIX Architecture Manual (AM016).

NoC, AI Engine, and DDR Memory Controller Clocks

The PMC includes four programmable clock dividers with outputs routed to the PL for general purpose use. The PMC also includes programmable clock divider outputs for the NoC, AI Engine, and DDR memory controllers.

PL Clocks

The PL includes its own clock arrays that are programmed when blocks are instantiated. The PL also includes programmable clock modules that can be driven by clocks from input pins and other sources.

The PMC clock controller includes four sets of reference clock dividers whose output is routed to the PL.

I/O Transceiver Clocks

There are local PLLs in the XPIO banks (for the PL, XPHY, and DDRMC) and the gigabit transceivers (GT). These high-speed I/Os use PLL clocks for precision I/O timing. These I/O buffers and transceivers are introduced in the Device I/O Connectivity chapter of the Hardware Architecture section. The I/O transceiver clocks are described in their associated documents:

  • GTY and GTYP transceiver PLLs: Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
  • XPIO bank XPLLs: Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Clock Register Modules

The individual clock controls are managed by the PLM firmware. The PLM writes to the clock and reset register modules.

  • CRP : device-level and individual PMC block clock control registers
  • CRL : subsystem and individual LPD block clock control registers
  • CRF : subsystem and individual FPD block clock control registers
  • CPMx_CRX: individual CPM block clock control registers