Two-way coherency enables a host transaction to snoop another attached cache.
Reads can hit or miss in the other cache. A miss is forwarded to system memory. A hit in the other cache returns the data memory from the other cache.
Writes can hit or miss in the other cache. The action taken by the CCI can have several effects depending on the AxCACHE attribute setting. These are listed in the AxCACHE section.
The 128-bit PL_ACE_FPD two-way coherent interface allows a PL interface host to snoop the APU L2 cache and it allows the APU L2 cache and ACE Lite interfaces to snoop the PL cache. This interface from the PL to PS provides full two-way hardware coherency between the APU MPCore and a processor or DMA unit in the PL.
The PL_ACE_FPD interface uses the full ACE protocol. This is an extension to the AXI protocol to provide hardware cache coherency.