Port Descriptions - 6.0 English

Clocking Wizard LogiCORE IP Product Guide (PG065)

Document ID
PG065
Release Date
2022-04-20
Version
6.0 English

Table: Clocking Wizard I/O describes the input and output ports provided from the clocking network. All ports are optional, with the exception being that at least one input and one output clock are required. The options selected determine which ports are actually available to be configured. For example, when Dynamic Reconfiguration is selected, these ports are exposed. Any port that is not exposed is appropriately tied off or connected to a signal labeled unused in the delivered source code.

Table 2-1: Clocking Wizard I/O

Port (5)

I/O

Description

Input Clock Ports (1)

clk_in1

I

Clock in 1 : Single-ended primary input clock port. Available when single-ended primary clock source is selected.

clk_in1_p

I

Clock in 1 Positive and Negative : Differential primary input clock port pair. Available when a differential primary clock source is selected.

clk_in1_n

clk_in2 (2)

I

Clock in 2: Single-ended secondary input clock port. Available when a single-ended secondary clock source is selected.

clk_in2_p (2)

I

Clock in 2 Positive and Negative: Differential secondary input clock port pair. Available when a differential secondary clock source is selected.

clk_in2_n (2)

clk_in_sel (2)

I

Clock in Select: When 1, selects the primary input clock; when 0, the secondary input clock is selected. Available when two input clocks are specified.

clkfb_in

I

Clock Feedback in: Single-ended feedback in port of the clocking primitive. Available when user-controlled on-chip, user controller-off chip, or automatic control off-chip feedback option is selected.

clkfb_in_p

I

Clock Feedback in: Positive and Negative: Differential feedback in port of the clocking primitive. Available when the automatic control off-chip feedback and differential feedback option is selected.

clkfb_in_n

Output Clock Ports

clk_out1

O

Clock Out 1: Output clock of the clocking network. clk_out1 is not optional.

clk_out1_ce

I

Clock Enable: Clock enable pin of the output buffer. Available when BUFGCE or BUFHCE or BUFR or BUFGCE_DIV buffers are used as output clock drivers.

clk_out1_clr

I

Counter reset for divided clock output: Available when BUFR or BUFGCE_DIV buffer is used as output clock driver.

clk_out[n] (3)

O

Clock Out[n]: Optional output clocks of the clocking network that are user specified. n can range in value from 2 to 7. For an MMCM, up to seven are available. For UltraScale™ PLLE3, up to two clocks are available and for 7 series/Zynq®-7000 PLLE2, up to six clocks are available.

clk_out[n]_ce (3)

I

Clock Enable: Clock enable pin of the output buffer. Available when BUFGCE or BUFHCE or BUFR or BUFGCE_DIV buffers are used as output clock drivers. n can range in value from 2 to 7.

clk_out[n]_clr (3)

I

Counter reset for divided clock output: Available when the BUFR buffer is used as output clock driver. n can range in value from 2 to 7.

clkfb_out

O

Clock Feedback Out: Single-ended feedback port of the clocking primitive. Available when the user-controlled feedback or automatic control off chip with single-ended feedback option is selected.

clkfb_out_p

O

Clock Feedback Out: Positive and Negative: Differential feedback output port of the clocking primitive. Available when the user-controlled off-chip feedback and differential feedback option is selected.

clkfb_out_n

O

Dynamic Reconfiguration Ports

daddr[6:0]

I

Dynamic Reconfiguration Address: Address port for use in dynamic reconfiguration; active when den is asserted.

dclk

I

Dynamic Reconfiguration Clock: Clock port for use in dynamic reconfiguration.

den

I

Dynamic Reconfiguration Enable: Starts a dynamic reconfiguration transaction. Refer to DRP protocol details for more information.

di[15:0]

I

Dynamic Reconfiguration Data in: Input data for a dynamic reconfiguration write transaction; active when den is asserted.

do[15:0]

O

Dynamic Reconfiguration Data Out: Output data for a dynamic reconfiguration read transaction; active when drdy is asserted.

drdy

O

Dynamic Reconfiguration Ready: Completes a dynamic reconfiguration transaction.

dwe

I

Dynamic Reconfiguration Write Enable: When asserted, indicates that the dynamic reconfiguration transaction is a write; active when den is asserted.

Dynamic Phase Shift Ports (2)

psclk

I

Dynamic Phase Shift Clock: Clock for use in dynamic phase shifting.

psen

I

Dynamic Phase Shift Enable: Starts a dynamic phase shift transaction.

psincdec

I

Dynamic Phase Shift increment/decrement: When 1, increments the phase shift of the output clock, when 0, decrements the phase shift.

psdone

O

Dynamic Phase Shift Done: Completes a dynamic phase shift transaction.

Status and Control Ports (4)

reset/resetn

I

Reset (active-High)/Resetn (active-Low): When asserted, asynchronously clears the internal state of the primitive, and causes the primitive to re-initiate the locking sequence when released.

power_down

I

Power Down: When asserted, places the clocking primitive into a low power state, which stops the output clocks.

input_clk_ stopped

O

Input Clock Stopped: When asserted, indicates that the selected input clock is no longer toggling.

locked

O

Locked: When asserted, indicates that the output clocks are stable and usable by downstream circuitry.

cddcreq (6)

I

Clock Divide Dynamic Change (CDDC) request. This is asserted after last DRP request is performed, and then deasserted after the last DRDY.

cddcdone (6)

O

Clock Divide Dynamic Change (CDDC) done. When output counters are updated, this signal is asserted.

s_axi_aclk

I

AXI Clock.

s_axi_aresetn

I

AXI Reset, active-Low.

s_axi_awaddr[10:0]

I

AXI Write address. The write address bus gives the address of the write transaction.

s_axi_awvalid

I

Write address valid. This signal indicates that a valid write address and control information are available.

s_axi_awready

O

Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

s_axi_wdata[31:0]

I

Write data.

s_axi_wstb[3:0]

I

Write strobes. This signal indicates which byte lanes to update in memory.

s_axi_wvalid

I

Write valid. This signal indicates that valid write data and strobes are available.

s_axi_wready

O

Write ready. This signal indicates that the slave can accept the write data.

s_axi_bresp[1:0]

O

Write response. This signal indicates the status of the write transaction

00 = OKAY (normal response)

10 = SLVERR (error condition)

11 = DECERR (not issued by core)

s_axi_bvalid

O

Write response valid. This signal indicates that a valid write response is available.

s_axi_bready

I

Response ready. This signal indicates that the master can accept the response information.

s_axi_araddr[10:0]

I

Read address. The read address bus gives the address of a read transaction.

s_axi_arvalid

I

Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledgment signal, s_axi_arready, is High.

s_axi_arready

O

Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

s_axi_rdata[31:0]

O

Read data.

s_axi_rresp[1:0]

O

Read response. This signal indicates the status of the read transfer.

00 = OKAY (normal response)

10 = SLVERR (error condition)

11 = DECERR (not issued by core)

s_axi_rvalid

O

Read valid. This signal indicates that the required read data is available and the read transfer can complete.

s_axi_rready

I

Read ready. This signal indicates that the master can accept the read data and response information.

s_axis_aclk

I

The global clock signal. All streaming signals from Read interface of the FIFO are sampled on the rising edge of s_axis_aclk.

Clock Monitor Ports (7)

ref_clk

I

This is the input reference clock used to monitor the user clocks. It is considered to be stable and error free.

user_clk0

I

User clock 0. This port is disabled when the ENABLE_PLL/MMCM0 checkbox is enabled in the Vivado IDE.

user_clk1

I

User clock 1. This port is disabled when the ENABLE_PLL1/MMCM1 checkbox is enabled in the Vivado IDE.

user_clk2

I

User input clock 2 to monitor.

user_clk3

I

User input clock 3 to monitor.

clk_stop[3:0]

O

The bits for this port are High when clock is stopped on the respective user clock.

Bit 0 - User clock 0

Bit 1 - User clock 1

Bit 2 - User clock 2

Bit 3 - User clock 3

clk_oor[3:0]

O

The bits for this port are High when input clock frequency is out of range than expected.

Bit 0 - User clock 0

Bit 1 - User clock 1

Bit 2 - User clock 2

Bit 3 - User clock 3

clk_glitch[3:0]

O

The bits for this port are High where there is a glitch in the input clock.

Bit 0 - User clock 0

Bit 1 - User clock 1

Bit 2 - User clock 2

Bit 3 - User clock 3

interrupt

O

This port gives the interrupts of the clock monitor feature.

Notes:

1. At least one input clock is required; any design has at least a clk_in1 or a clk_in1_p/clk_in1_n port.

2. Not available when primitive chosen is UltraScale PLL or Spread Spectrum is selected for MMCM.

3. The clk_out3 and clk_out4 ports are not available when Spread Spectrum is selected.

4. Exposure of every status and control port is individually selectable.

5. This version of Clocking Wizard supports naming of ports as per requirements. The list mentioned in Table: Clocking Wizard I/O is the default port list.

6. Ports used for dynamic change of output counter without reset. Available only in MMCME3 primitive.

7. These ports are available when the Clock Monitor feature is enabled.

8. The user must write to the interrupt enable register with all 1's (i.e., interrupt enable for clock stop, clock overrun, and clock underrun bits in the interrupt status register) for the Interrupt to be enabled.