The available clocking features are shown for the selected target device. You can select as many features as desired; however, some features consume additional resources, and some can result in increased power consumption. Additionally, certain combinations of features are not allowed.
When using IP integrator, the frequency, phase and clock domain properties of the output clocks are automatically propagated and any change in input clock properties reflects on all the outputs.
Note: The Port Renaming tab has been removed from the Clocking Wizard interface because the IP does not support renaming of the ports in IP integrator.
Details of the clocking options are listed below:
• Frequency Synthesis allows output clocks to have different frequencies from the active input clock.
• Spread Spectrum provides modulated output clocks, which reduces the spectral density of the electromagnetic interference (EMI) generated by electronic devices. This feature is available for the MMCM(E2/E3/E4)_ADV primitive only. The Minimize Power and Dynamic Reconfig features are not available when Spread Spectrum is selected.
• Phase Alignment allows the output clock to be phase locked to a reference, such as the input clock pin for a device. The default value of phase alignment is set to false for UltraScale and UltraScale+ primitives. This feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used.
RECOMMENDED: Use this feature only if you specifically require it. Extra clock routes can be used by implementation tools for high fanout signals instead of the Phase Alignment feature.
Note: The Phase Alignment option is not available for the UltraScale PLL primitive.
• Minimize Power allows you to minimize the amount of power needed for the primitive. This is at the possible expense of frequency, phase offset, or duty cycle accuracy.
• Dynamic Phase Shift allows you to change the phase relationship on the output clocks.
• Dynamic Reconfiguration allows you to change the programming of the primitive after device configuration. When this option is chosen, the AXI4-Lite interface is selected by default for reconfiguring the clocking primitive. The DRP interface can be selected if direct access to MMCM/PLL DRP register is required. See Dynamic Reconfiguration through AXI4-Lite for more information.
• Selecting Balanced results in the software choosing the correct bandwidth for jitter optimization.
• Minimize Output Jitter . This feature minimizes the jitter on the output clocks, but at the expense of power and possibly output clock phase error. This feature is not available with the Maximize input jitter filtering feature.
• Maximize Input Jitter filtering allows for larger input jitter on the input clocks, but can negatively impact the jitter on the output clocks. This feature is not available with the Minimize output jitter feature.
• Safe Clock Startup enables a stable and valid clock at the output using BUFGCE after Locked is sampled High for eight input clocks. The sequencing feature enables clocks in a sequence according to the number entered in the IDE. The delay between two enabled output clocks in sequence is eight cycles of the second clock in the sequence clock. This feature is useful for a system where modules need to start operating one after the other.
• Optimize Clocking Structure . This option is only available to the user for the MMCM and PLL primitives. When this option is enabled, the IP generates the optimal clocking structure for the explicit primitive in combination with the auto buffer selection.