Hard Block Planner - 2022.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID: UG899
Release Date: 2022-10-19
Version: 2022.2 English

Introduction
Navigating Content by Design Process
I/O and Clock Planning Stages‌
I/O and Clock Planning Design Flow
Pre-RTL I/O Planning
RTL I/O Planning
Netlist I/O Planning
Final I/O Validation with an Implemented Design
I/O and Clock Planning Design Flow Steps
I/O and Clock Planning Features
I/O and Clock Planning Using the Platform Board Flow‌
I/O and Clock Planning for SSI Technology Devices‌
I/O and Clock Planning for IP with I/O Ports‌
I/O Planning for Zynq UltraScale+ MPSoCs‌
I/O Planning for UltraScale and UltraScale+‌
I/O Planning for Versal ACAP
Configuring the Device
Defining Alternate Compatible Parts‌‌
Tcl Command Example for Defining Alternate Compatible Parts
Setting Device Configuration Modes
Tcl Command Example for Setting Device Configuration Modes
Setting Device Constraints‌‌
Creating a DCI_CASCADE Constraint
Tcl Command Example for Creating a DCI_CASCADE Constraint
Modifying or Removing DCI Cascade Constraints
Creating an INTERNAL_VREF Constraint
Tcl Command Example for Creating an INTERNAL_VREF Constraint
Setting the Configuration Bank Voltage Select Pin‌
I/O Logic and Low-Speed I/O Planning‌
Using the I/O Planning View Layout‌
Viewing Device Resources
Properties
Clock Region Resources and Statistics
I/O Bank Resources
Multifunction Pins
Defining and Configuring I/O Ports
Importing I/O Ports
Importing a CSV File
Importing an XDC File
Creating Single-Ended or Differential I/O Ports
Tcl Command Examples for Creating Single-Ended or Differential I/O Ports
Making and Splitting Differential Pairs
Tcl Command Examples for Making and Splitting Differential Pairs
Configuring I/O Ports
Setting I/O Port Direction
Creating I/O Port Interfaces
Adding I/O Ports to an Interface
Removing I/O Ports from an Interface
Tcl Command Examples for Working with I/O Port Interfaces
Automatically Inferring I/O Port Interfaces
Tcl Command Examples for Working with the Platform Board Flow
Prohibiting I/O Pins and I/O Banks
Tcl Command Example for Prohibiting I/O Pins
Placing I/O Ports
Placing I/O Ports Sequentially
Placing I/O Ports into I/O Banks
Tcl Command Examples for Placing Ports into I/O Banks
Placing I/O Ports in a Defined Area
Swapping Previously Placed I/O Ports
Moving Previously Placed I/O Ports
Automatically Placing I/O Ports‌
Placing Gigabit Transceiver I/O Ports
Removing I/O Placement Constraints
Migrating an I/O Planning Project to an RTL Project
I/O Planning for UltraScale Architecture Memory IP
UltraScale Architecture Memory IP I/O Planning Design Flow Changes
Consolidated I/O Planning
PHY Implementation
Configuring Memory IP
Generating IP Output Products
UltraScale Architecture Memory IP I/O Planning in the Vivado IDE
UltraScale Architecture Memory IP I/O Planning in the Elaborated Design
Using the Memory Bank/Byte Planner
Manually Assigning Signal Groups
Automatically Assigning Signal Groups
Understanding Warnings for Assigned Non-Memory Ports
Unplacing Signal Groups and Controllers
Modifying Memory I/O Ports‌
Modifying Ports in the I/O Ports Window
Modifying Ports in the Package Pins Window
Running Memory DRCs
Implementing the PHY
Tcl Command Example for Implementing the PHY
Copying I/O Port Assignments Between Designs
High-Speed I/O Planning for Versal ACAP
Using the Advanced IO Planner
Hard Block Planner
Hard Block Planning for Versal ACAP
Using the Hard Block Planner
Clock Planning‌‌
Locating Logic Cells
Placing Clock Logic in the Device Window
Validating I/O and Clock Planning
Running DRCs‌‌
Running I/O Port and Clock Logic Related DRCs
Tcl Command Example for Running DRCs
Tcl Command Example for Defining a Custom Rule Deck
Enabling or Disabling Interactive DRCs
Viewing DRC Violations
Sorting DRC Violations
Viewing DRC Violation Properties
Creating Custom DRCs
Querying DRCs
Report Methodology
Working with SSN Analysis‌‌
Determining SSN Analysis Support
Running SSN Analysis
Viewing SSN Results
Viewing I/O Bank Properties in SSN Results
Improving SSN Results
Adding Phase Information to SSN Analysis
Adding Temperature Information to SSN Analysis for 7 Series Devices
Interfacing with the System Designer
Exporting I/O Pin and Package Data‌‌
Generating IBIS Models‌
Exporting IBIS Models
Interfacing with the PCB Design
Part Compatibility
DRC
SSN Analysis
IBIS Simulation
Package Trace Length‌
CSV Export
Supported Third-Party PCB Tools
Using I/O Port Lists in CSV File Format‌‌
CSV File‌
Differential Pairs in the CSV File‌‌
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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