The Versal XPIO IOLOGIC contains the IDDR, IFD, IDELAY, ODDR, OFD and ODELAY.
When multiple clocks are routed into an IOLOGIC, and a local inversion is required on one or more of the clocks in the IOLOGIC, a Vivado issue can cause incorrect inversion of the clock in the IOLOGIC.
The local inversion is determined during the implementation steps and therefore the issue is design run dependent. If the implementation tool does not use a local inversion for the IOLOGIC clock, then the issue is not seen.
If the incorrect local inversion is programmed for the IOLOGIC, the data will be captured on the opposite edge than was expected and this can cause incorrect data clock alignment.
This issue was found in the 2021.1 version, but applies to all Vivado versions supporting Versal families.