Solution

000034466 - 2022.2 (and prior) Vivado: Versal XPIO IOLOGIC might invert capture clock

Release Date
2022-11-17
Revision
1.0 English

To check if a design has the incorrect programming of the local clock inversion in IOLOGIC, you can run the script provided.

source -notrace pre_bitream.tcl 

The script will automatically correct the inversion programming if an issue is found and should be run before the device image is generated. 
cells driven by XPIOLOGIC_X82Y2/GCLK_SIG_1_ have incorrect inversion in PDI
inverting cloc k pins on cell rx_data_in
found cell of type IDDRE1
flip IS_C_INVERTED
flip IS_CB_INVERTED
There will be no output from the script when there are no issues found. 

Note: Timing analysis should be run before the script is applied. The pdi / write_device_image should be run after the script has been applied.

If timing is rerun after the script, it will appear in the timing that there is an additional inverter in the clock path. This will result in an incorrect timing analysis.