The Zynq UltraScale+ PS MIO might output a High glitch during the power-up ramp of the VCCO_PSMIO supply.
If the issue occurs, the MIO has been observed to begin driving High when the VCCO_PSMIO supply ramps to 0.4V-0.5V and continues to drive High until the VCCO_PSMIO reaches 0.6V – 1.4V, before the MIO returns to a high-impedance state.
Actual occurrence on a specific device or specific MIO is non-deterministic and the actual output glitch profile likely depends on the device/MIO, temperature and VCCO_PSMIO power ramp profile. See the example MIO glitch shown in the yellow waveform below where the blue waveform is the example VCCO_PSMIO ramp.
No settings or reasonable external pull-down can control/overcome this output glitch.
Figure 1: Ch3(blue)=VCCO_PSIO and Ch4(red)=MIO with external 2.2kohm pull-down to GND.
Configurations Affected:
The issue affects PS MIOs that are either pulled or driven low during power-up. PS MIO in all Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices can exhibit this issue. The occurrence of the issue is not deterministic.
In one study, the issue occurred in ~75% of devices and, in affected devices, the issue occurred on 10-33% of MIO, depending on the device and condition.
The issue can occur during the VCCO_PSMIO ramp of the recommended power-on sequence: VCC_PSINT* ramp-up, followed by VCC_PSAUX ramp-up, followed by VCCO_PSIO ramp-up. Alternate power-on sequences might incur other kinds of glitches due to non-deterministic values of internal control logic.
Note: the glitch does not occur when VCC_PSAUX and VCCO_PSIO are supplied from the same 1.8V source.
Impact: The MIO glitch might incur signal contention, including to bused signals, or cause other devices to detect a temporary High from a connected Zynq UltraScale+ PS MIO.