Because the PS MIO glitch occurs during the power-on sequence and because Zynq UltraScale+ requires a PS_POR_B input signal that is Low through the power-up sequence, the PS_POR_B signal can be leveraged for work-arounds.
For example:
- Use PS_POR_B to disable or to keep other connected devices in reset, which can prevent other devices from reacting to a potential PS MIO glitch.
- Use PS_POR_B with an external circuit to gate the PS MIO logic signal and prevent a possible glitch from affecting sensitive buses or device inputs.
- Q: Does this issue occur on 1.8V PS MIO and 3.3V PS MIO?
- A: Yes. The glitch occurs when VCCO_PSIO is within ~0.4V - ~1.4V and this condition occurs during power-up for PS MIO that is eventually operated at 1.8V and 3.3V PS MIO. However, if VCCO_PSIO is supplied from the same 1.8V source as VCC_PSAUX, the PS MIO glitch does not occur.
- Q: Does this issue impact device/pin reliability?
- A: No. The I/O has been verified against EM and aging for the product lifetime. Lifetime verification conditions surpass the glitch exposure/condition.
- Q: Can a PS MIO, that is driven or pulled High to VCCO_PSIO, have a drive-Low glitch?
- A: No.
- Q: What is the equivalent series resistance of the drive-High glitch?
- A: The glitch drives from the VCCO_PSIO rail with an equivalent series resistance of 50 ohms (measured from a sample simulation).