72992 - Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Possible link training failures or data errors on PCIe, SATA, or USB 3.0 protocol links using PS GTR

Release Date

An updated fix is available in Vivado 2021.1. All customers are required to update their designs if they use the below protocols with PS GTR. For customers in Production in previous versions of Vivado, a patch can be provided.

  • PCIe / USB 3.0 / SATA GEN2 / SATA GEN3
    • Fix is available in Vivado 2021.1
    • Revision 3 of the patch for Vivado releases from 2017.2 to 2020.3 are attached to this Article.

Note:  After applying the patch you must use the reset_project command in Vivado and rerun PCW on your Vivado design to enable the fix.

No hardware changes are made so the bitstream does not need to be updated.

Embedded Software must be rebuilt after running PCW to enable the fix. 

To verify that the patch has been applied correctly, make sure the below text is included in your psu_init.c file.
static int serdes_illcalib

Previous patches (for earlier Vivado versions) were found to have some of the issues listed below.  These issues have been addressed in the current patch release.

  • Issue 1 - A write to OCM as part of the fix caused boot failures for some boot solutions. If this issue impacted your system you will observe boot failures when loading the FSBL
  • Issue 2 - When SATA was used for certain configurations, link failures were observed. This was a functional issue with the patch where some incorrect settings were propagated and the SATA link would fail at boot.
  • Issue 3 - If there was a combination of PCIe and DisplayPort/USB/GEM or a combination of SATA and DisplayPort/USB/GEM, link failures could be observed on the DisplayPort, USB or GEM links.  The issue was caused by redundant PLL lock checks in the fix extending the calibration time and resulting in protocol timeouts. The following combinations are affected:
 At least one laneAt least one lane
CombinationPCIe or SATADisplayPort, USB, GEM
  • Issue 4 - Boot times are extended due to changes in the fix in configurations with both SATA and PCIe links. Boot time can increase by 200-300 ms for any configuration combining SATA and PCIe or where all four lanes are configured as PCIe. Xilinx measurements were made on a system with the APU Clock running at max - 1200 MHz. For systems running a slower clock, the boot time might be greater than the  above.
Below is the list of patches which need to be reviewed and possibly replaced with the new patch release based on the Xilinx recommendations provided below.

 Xilinx Recommendations:

  • Scenario 1 - User has not applied any fix for this issue
    • Xilinx Recommendation - For new designs, upgrade to the 2021.1 release. For Designs in Production, apply the attached patch for the relevant version of Vivado.
  • Scenario 2 - User has applied a previous version of the patch listed above and is impacted by any issue listed
    • Xilinx Recommendation - For new designs, upgrade to the 2021.1 release. For Designs in Production, apply the attached patch for the relevant version of Vivado.
  • Scenario 3 - User has applied a previous patch and is not impacted by the issues listed
    • Xilinx Recommendation - No update needed.

Additional System Considerations:

For all systems using SATA or PCIe, the GT Ref Clock must be present and stable from the beginning of the boot process.

This can have a similar failure mechanism to the issue described above. This requirement should also be checked. Link failures can be observed with and without the patch if this requirement is not met. If your system cannot meet this requirement, please contact Technical Support.

For more information on this issue or for patch requests, please contact Xilinx Technical Support:

Revision History:

12/20/2019Initial Release
01/10/2020Latest Update
06/05/2020Latest Update
11/27/2020Latest Update
11/03/2021Latest Update