76685 - Design Advisory, Versal ACAP, XPE - Power Supply Sequence Change

Release Date

This Design Advisory covers Versal Devices. For more information on how to sign up to receive notifications of new Design Advisories, see (Xilinx Answer 18683)

For all Versal devices, starting in XPE 2021.2, the power sequence on the XPE Power Design Tab has moved the VCCO supply rails to ramp first within their respective power supply sequencing domain with some optimizations.


If the required power sequence is not used, intermittent boot errors or hangs during warm restarts (any restart that does not first perform a power cycle) can occur.

Warm restarts include but are not limited to the following use cases:
  • External POR_B pin assertion
  • Internal/External SRST
  • Watchdog timer reset
  • MultiBoot
  • Tandem boot
  • PLM Error management

For example, an error during PLM when configuring hardened peripherals such as DDRMC timeout or a GT address exception might occur, indicating a timeout during configuration:

XPlmi_MaskPoll: Addr: 0xF6110008,  Mask: 0x10, ExpVal: 0x10, Timeout: 1000000 ...ERROR

Received Exception
MSR: 0x00000702, EAR: 0xF6890000, EDR: 0x00000000, ESR: 0x00000064,
R14: 0xF020CA78, R15: 0xF022F1C4, R16: 0x00000000, R17: 0xF0213DB4