Solution

76685 - Design Advisory, Versal ACAP, XPE - Power Supply Sequence Change

Release Date
2022-02-21

Resolution

This issue has been corrected in the XPE Power Supply Guidelines in the 2021.2 release and later.

Work-around

Xilinx strongly recommends following the updated supply sequence. For customers not able to change the power sequence, a limited work-around is available. The limited work-around greatly reduces the time frame where this is issue can be triggered to the time between loading of the .rnpi partition until the end of loading the first PDI image containing a PL partition.

A work-around without this limitation is currently planned for Vivado 2022.1.

Vivado 2021.2
The limited work-around can be enabled via a property on the CIPS IP instance via the Vivado Tcl console (assuming versal_cips_0 instance name):

set_property -dict [list CONFIG.PS_PMC_CONFIG {PS_USE_MJTAG_TCK_TIE_OFF {1}}] [get_bd_cells versal_cips_0]

Vivado 2021.1
A patch is attached below for the 2021.1 release which also requires a small Verilog module and .xdc constraints to be added to the user design.

See the vivado/patch_readme folder for additional documentation and the design files.

Revision History:

12/14/21 - Simplified with 2021.2 XPE availability
10/29/21 - Added 2021.2 workaround, updated patch revision
09/30/21 - Initial Release