Resolution
This issue has been corrected in the XPE Power Supply Guidelines in the 2021.2 release and later.
Work-around
Note: AMD Xilinx strongly recommends following the updated supply sequence.
Vivado 2022.1 and later
In the Vivado Tcl console, set the following parameter to enable a work-around .cdo to be added to the .bif file:
set_param project.enableMjtagCdo 1
Vivado 2021.2
For customers who are unable to change the power sequence, a limited work-around is available. This limited work-around greatly reduces the time frame where this issue can be triggered to the time between loading of the .rnpi partition until the end of loading of the first PDI image containing a PL partition.
The limited work-around can be enabled via a property on the CIPS IP instance via the Vivado Tcl console (assuming versal_cips_0 is the instance name):
set_property -dict [list CONFIG.PS_PMC_CONFIG {PS_USE_MJTAG_TCK_TIE_OFF {1}}] [get_bd_cells versal_cips_0]
Vivado 2021.1
The attached Vivado patch and PLM software patch can be used for the Vivado 2022.1 work-around.
See the vivado/patch_readme folder for additional installation directions for the Vivado patch. For the PLM patch installation, see the Xilinx Wiki - Petalinux Yocto Tips. In the Vivado Tcl console, set the following parameter to enable a workaround .cdo to be added to the .bif file:
set_param project.enableMjtagCdo 1
Revision History:
02/16/23 - Added 2022.1 and 2021.1 workarounds and consolidation note
12/14/21 - Simplified with 2021.2 XPE availability
10/29/21 - Added 2021.2 workaround, updated patch revision
09/30/21 - Initial Release