To work around this issue you can use the following options:
1) Set VCCO_503=1.8V.
Note: if using an SSIT device, please contact Xilinx Technical Support.
2) When VCCO_503 must be 2.5V or 3.3V, an alternate TAP state path for entering the Shift IR or Shift DR state can be used to avoid the issue as shown below.
In Vivado 2021.2, (and later software versions) the tool auto-detects and uses the alternate TAP state paths by default when a Versal device is in the JTAG chain.
In the 2021.2 release (and later software versions) the user can also manually start hw_server with the following command:
hw_server -e "set jtag-pause-before-shift 2"
In XSDB 2021.2, (and later software versions) the configparam command must be applied after "connect" using the following:
xsdb% configparam jtag-pause-before-shift 2
This alternate path only shows the entry to the shift DR state. The same should also be used for the shift IR state.
The above configparam applies the work-around to both Shift-DR and Shift-IR operations.
3) Request this alternate TAP state path JTAG work-around from your JTAG tool vendor when VCCO_503 must be 2.5V or 3.3V.