76889 -Versal HDIO/MIO: When powered at 3.3V or 2.5V a race condition can exist between data and tristate when using a tristate is a Design Advisory for Versal ACAPs which details the MIO and HDIO requirements when tristate control is changing.
This Article discusses the JTAG EXTEST use case with PS MIO and PL HDIO operating at 3.3V or 2.5V.
PS MIO and PL HDIO Banks powered at 2.5V or 3.3V and using JTAG EXTEST mode (irrespective of VCCO_503 voltage level) for a board interconnect test could be affected by the tristate-data race condition, if a JTAG EXTEST test vector changes the 3.3V/2.5V HDIO tristate and data in the same test vector.
The JTAG EXTEST function is used at manufacturing for board-level interconnect tests by third-party JTAG test tools.
Xilinx Lab tools do not use the JTAG EXTEST function and therefore are not affected by this EXTEST issue.
Arm processor JTAG cable-based debug tools do not use the JTAG EXTEST function and therefore are not affected by this EXTEST issue.
Note: See Answer Record 76893 - Versal : JTAG TDO for a closely related Versal JTAG TDO issue.
This Article discusses the JTAG EXTEST use case with PS MIO and PL HDIO operating at 3.3V or 2.5V.
PS MIO and PL HDIO Banks powered at 2.5V or 3.3V and using JTAG EXTEST mode (irrespective of VCCO_503 voltage level) for a board interconnect test could be affected by the tristate-data race condition, if a JTAG EXTEST test vector changes the 3.3V/2.5V HDIO tristate and data in the same test vector.
The JTAG EXTEST function is used at manufacturing for board-level interconnect tests by third-party JTAG test tools.
Xilinx Lab tools do not use the JTAG EXTEST function and therefore are not affected by this EXTEST issue.
Arm processor JTAG cable-based debug tools do not use the JTAG EXTEST function and therefore are not affected by this EXTEST issue.
Note: See Answer Record 76893 - Versal : JTAG TDO for a closely related Versal JTAG TDO issue.