Solution

JTAG EXTEST is the primary JTAG function used for board manufacturing interconnect testing. Board interconnect test vectors for the EXTEST function are typically auto-generated by JTAG board test tools.

Some JTAG test tools also use the JTAG EXTEST function to test or program components attached to Versal pins. The impact of this issue on JTAG board interconnect tests or on application-specific JTAG test tool functions depend on the JTAG test tool’s test vector generator.

See the below list of JTAG test tools with known conditions of impact.

All Versal device EXTEST-related functions are affected, including the following Versal device JTAG instructions: EXTEST, EXTEST_PULSE, EXTEST_TRAIN, and PRELOAD.

Work-around:

If your JTAG test tool’s generated board interconnect EXTEST test vectors do not avoid the simultaneous tristate control and data change or if unknown, then one of the following work-arounds is recommended:

Work-around 1 - Automated avoidance of PS MIO and PL HDIO output tristate switching: 

Download the Versal device BSDL model files from https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/bsdl-models/versal.html
Use the <device>_<package>_AR76889_workaround.bsd files from the download .zip for the affected device to work-around the issue.

Notes: 

- Because the operating voltage is known by the BSDL model, the work-around BSDL files conservatively keep all PS MIO bank and PL HDIO bank outputs in tristate regardless of the bank operating voltage.
- Because PS MIO and PS MIO and PL HDIO outputs are removed from board interconnect testing, these outputs should be instead be covered with functional tests.

Work-around 2  - Manual avoidance of PS MIO and PL HDIO output tristate switching:

When using JTAG EXTEST, keep all PS MIO and PL HDIO outputs in 3.3V or 2.5V banks disabled by keeping the tristate control cell value equal to its safe value (see the BSDL file for control cell safe values) or by marking the affected PS MIO and PL HDIO pins to be excluded from the boundary-scan tests in the boundary-scan test tool.

Do not use EXTEST to test or drive PS MIO or PL HDIO output pins in 3.3V or 2.5V banks.

In JTAG board test tools, prevent the tool from generating test vectors for 3.3V or 2.5V HDIO pins that drive an output value from these pins.

Instead, cover affected PS MIO and LP HDIO board interconnects with functional tests.

About Xilinx Versal device PS MIO and PL HDIO pins:

I/O pins in a Versal device are grouped into I/O banks. Each bank contains a particular type of I/O pin and all I/O pins belonging to the bank are powered from a common bank VCCO power supply pin. I/O banks in the Versal device are identified by a three-digit bank number.

• PS MIO banks are numbered 500, 501, 502, and 503, and power supplies for each are VCCO_500, VCCO_501, VCCO_502, and VCCO_503 respectively.
• PL HDIO banks are numbered 3## or 4##, where ## is two decimal digits. Power supplies for each are VCCO_3## or VCCO_4##, respectively. For example, for bank 306 or bank 406, power supplies are VCCO_306 or VCCO_406 respectively. Note: Some packages do not have PL HDIO banks.

I/O pin, bank number, and bank power pin details for each device-package can be found in the Versal ACAP Package Pinout files at https://www.xilinx.com/support/package-pinout-files/versal-pkgs.html

Use the following steps to determine whether a pin is a PS MIO pin or a PL HDIO pin and at which voltage the pin is operating:

1. To find PS MIO or PL HDIO pins, use one of the following to find/determine pins from the board schematic:
   1. Find Versal device schematic symbol pin names. If the symbol preserves the Xilinx pin name, then the format of an HDIO pin name is:
      1. PS MIO pin name format: PMC_MIO##_5## or LPD_MIO##_5##, where the "MIO" indicates a PS MIO pin and the 5## indicates the bank number.
      2. PL HDIO pin name format: IO_<name>_###, where if ### = a 3## or 4## bank number, then the pin is a PL HDIO pin in bank number 3## or 4##.
   2. Find a Versal device schematic symbol that indicates that a group of I/O and indicates the I/O group belongs to bank number 3## or 4## or 5##. All I/O pins in a bank numbered 3## or 4## are PL HDIO pins. All I/O pins in a bank numbered 5## are PS MIO pins.
   3. Find the Versal device pin number and look up the pin type/bank in the Versal ACAP Package Pinout file from https://www.xilinx.com/support/package-pinout-files/versal-pkgs.html 
2. To find the PS MIO or PL HDIO pin operating voltage, use one of the following to find/determine Versal device HDIO pins from the board schematic:
   1. Find Versal device schematic symbol power pins with the form VCCO_###, where ### represents a three-digit decimal number. If the symbol preserves the Xilinx power pin name, then VCCO_3##, VCCO_4##, or VCCO_5## is a power pin for a PL HDIO or PS MIO bank. Find the voltage supplied to these VCCO pins to determine the operating voltage of the pins in the bank.
   2. Find a Versal device schematic symbol that indicates a group of I/O and indicates the I/O group belongs to bank number 3##, 4##, or 5##. If the schematic symbol includes a pin that includes VCCO in the name, that is the power pin for the bank. Find the voltage supplied to the VCCO pin to determine the operating voltage of the pins in the bank.
   3. Find the VCCO_3##, VCCO_4###, and VCCO_5## power pins in the Versal ACAP Package Pinout file from https://www.xilinx.com/support/package-pinout-files/versal-pkgs.html, and find the voltage supplied to these VCCO pins to determine the operating voltage of the pins in the respective banks.

The following is a list of JTAG board test tools with known conditions of impact for this issue.

This list is not comprehensive. Check with your JTAG test tool vendor if they are not listed, or for application-specific functions:

• Goepel – Set the following two TestStep Parts options to avoid this EXTEST issue: Disable the DRShift Switch Pins option and DRShift Enable Pins option.
• JTAG Technologies – Not affected. JTAG Technologies test vector generator does not change tristate and data in the same vector. Therefore this tool is not affected by this EXTEST issue.
• XJTAG – Affected

For unlisted vendors or for specific tool applications, supply the vendor with a reference to this Answer Record and ask the following to determine if the vendor’s JTAG test tool avoids this issue or if affected by this issue, has a work-around available for this issue.

Note: If you are checking with a JTAG tool vendor about the impact of this issue, also ask the vendor to check for impact of the closely related JTAG TDO issue in 76893 - Versal: JTAG TDO if the Versal device TDO pins (bank 503, VCCO_503) are operating at 3.3V or 2.5V.

For JTAG tools using EXTEST on PS MIO or PL HDIO operating at 3.3V or 2.5V, the requirement to the avoid this issue is as follows:

An EXTEST vector must not change a PS MIO or PL HDIO output tristate control value and output data value in the same EXTEST vector. More specifically, the following simultaneous changes must be avoided in an EXTEST vector:

• Avoid simultaneous change of tristate control cell 1-->0 and output data cell 0-->1
• Avoid simultaneous change of tristate control cell 0-->1 and output data cell 1-->0

Note: The default reset (initial) value of the cells is 1.

Work-around for using EXTEST with affected PS MIO and PL HDIO pins:

The following assumes an EXTEST instruction is loaded.

For a test that drives value V out of pin outputs (TXs), do the following:

1. Shift through BSCAN, tristating-disable values to TX-tristate BSCAN cell, along with V_bar to TX-data input BSCAN cell
2. Perform update_dr. This step is expected to cause the problem to appear if data changes
3. Go to shift_dr state
4. Shift through BSCAN, tristating-disable values to TX-tristate BSCAN cell (no change here), along with V to TX-data input BSCAN cell
5. Go to update_dr state
6. Run output tests
For an input test (i.e. to disable TX’s) do the following:

Assumption: starting from the reset state [I/O is tristated]
1. Shift through BSCAN, tristating-enable values to TX-tristate BSCAN cell, along with any V or V_bar to TX-data input BSCAN cell
2. Perform update_dr. This step is not expected to cause the problem to appear because tristate does not change (from the reset value)
3. Run the input test

Note: assuming outputs and inputs are tested together, it is okay to have duplicate input testing values in the second shift.