In Versal devices, for the MMCM and DPLL, all outputs using the phase detector deskew logic (CLKIN_DESKEW, CLKFB_DESKEW ports) will be incorrectly timed in Vivado 2021.1.1 and earlier versions.
| MMCM Feedback | Up to 2021.1.1 | 2021.2 | 2021.2.1 |
| Without Deskew | Supported | Supported | Supported |
| With CLKFBOUT Deskew | Supported | Supported | Supported |
| Using the Deskew Logic (CLKIN_DESKEW, CLKFB_DESKEW) | Patch Required | Supported for all on- chip configuration | Supported for all on-chip configuration |
For customers using CPM4 with the CPM to PL interfaces enabled please refer to 76947 - Versal ACAP CPM Mode for PCI Express (Vivado 2021.1) - Potential timing issue with designs that have CPM4 to PL interfaces enabled
For customers using the XPLL outside of the Advanced IO Wizard (inc MIPI) and Memory controller please refer to 76848 - 2021.2 Vivado Versal Clocking: XPLL Deskew and Production Software and Speed Specification Release Revised to Vivado tools 2021.2.1