Design Advisory for Versal ACAP SSIT devices: NoC configuration vulnerability

Release Date

This Design Advisory describes a vulnerability that can potentially lead to unauthorized access of PMC-RAM through an interposer breach on SSIT devices (such as XCVP1502, XCVP1552, XCVP1802, XCVH1582, XCVH1742, XCVH1782) and has its root in how the NoC is configured.

Because the NoC compiler (in Vivado 2021.2 and 2022.1) configures the NoC to allow PMC-RAM read/write requests to traverse SLRs, an attacker could for example hijack the interposer to inject writes to the NoC that modify PMC-RAM space.

The hijacking of the interposer is considered a rather sophisticated attack, albeit feasible.