MBUFG buffers utilize BUFDIV_LEAF route-thru BELs with a divider setting of 1, 2, 4, 8 to implement the divided clocks driven by the O1, O2, O3, O4 outputs of the MBUFG.
During route and post-route implementation stages Vivado might move clock loads from one BUFDIV_LEAF driver to another. When that happens, and a BUFDIV_LEAF ends up load-less, it can be utilized by Vivado as a route-thru or as a driver for another clock.
In the case where the re-used BUFDIV_LEAF requires a divide value of 1, the previous BUFDIV_LEAF divide value is retained which results in functional issues on HW when the previous divide value was not 1.
Vivado might use the bufdiv_leaf as a route-thru from the the clr_b to the 0 when there are multiple route_design runs and the path will not toggle in hardware.
This issue was found in the 2021.1 version, but applies to all Vivado versions supporting Versal families prior to 2022.1.2