Clocking

Alveo X3522PV Adaptable Accelerator Card User Guide (UG1607)

Document ID
UG1607
Release Date
2022-10-18
Revision
1.0 English

The card provides the following reference clocks:

  • PCIe® reference clocks
  • DDR4 Memory controller reference clock
  • User reference clock
  • Ethernet reference clocks

The following high-level clock tree shows the card advanced clocking and jitter attenuator logic. See the following figure for more details.

Figure 1. X3522PV Clocking Tree

The card uses the SiTime SiT95145AI clock generator to provide reference clocks for PCIe, user reference, and DDR memory controllers. The details are provided in the following table and the design constraints (XDC) file.

Table 1. Clock Generator Output Frequencies
SiTime SiT95145AI Clock Output Reference Frequency (MHz) Destination Block Reference Clock Schematic Net Names XDC Net Name
OUT0 300 FPGA Bank 66 DDR Memory Controller CLK2_LVDS_300_P

CLK2_LVDS_300_N

CLK2C_LVDS_300_P

CLK2C_LVDS_300_N

OUT1 Not Used
OUT2 Not Used
OUT3 161.1328125 FPGA Bank 231 DFSP28 CLK1_LVDS_161_P

CLK1_LVDS_161_N

CLK1C_LVDS_161_P

CLK1C_LVDS_161_N

OUT4 Not Used
OUT5 300 FPGA Bank 65 User CLK3_LVDS_300_P

CLK3_LVDS_300_N

CLK3C_LVDS_300_P

CLK3C_LVDS_300_N

OUT6 Not Used
OUT7 100 FPGA Bank 225 PCIe® Reference Clock

CLK0_LVDS_100P

CLK0_LVDS_100N

CLK0C_LVDS_100_P

CLK0C_LVDS_100_N