PCIe Reference Clocks

Alveo X3522PV Adaptable Accelerator Card User Guide (UG1607)

Document ID

UG1607

Release Date

2022-10-18

Revision

1.0 English

The following table describes the two clocks that are provided to support PCIe clocking.

Table 1. PCIe Reference Clocks
Clock Source	Description
PCIe Edge Connector	100 MHz clock originating from the PCIe edge connector and connected to GTY 225 MGTREFCLK0 inputs. The clock signal is AC coupled.
Internal clock generator	100 MHz clock originating from the SiTime SiT95145AI clock generator and connected to GTY 225 MGTREFCLK1 inputs. The clock signal is AC coupled and meets PCIe Gen3/Gen4 jitter specifications.