Power Limits

Alveo X3522PV Adaptable Accelerator Card User Guide (UG1607)

Document ID
UG1607
Release Date
2022-10-18
Revision
1.0 English

PCIe card electrical power limit is set by maximum current allowed for power connectors and worst-case rail voltage. Some portion of electrical power delivered to the card is lost in power distribution networks (PDN) and in power regulators. The card targets 2% loss for PDN and 8% loss (92% efficiency) for regulators at target 70W TDP load. The following table summarizes the card power budget available and the worst case total power available for a workload. It includes the worst case maximum power available for each power rail along with the tolerance.

Table 1. Card Electrical Power Limit Worksheet
Power Rail Volts (V) Max Amps (A) Tolerance Worst Case Max Power Available (W)
+3.3Vaux Edge Connector 3.3 0.375 +/-9% Used for SC and sensors.
+3.3V Edge Connector 3.3 3 +/-9% 9.0
+12V Edge Connector 12 5.5 +/-8% 60.7
PCIe Edge Connector ( +3.3V & +12V Edge) Power Budget       69.2
PDN Target Loss (2%)       1.4
VRM Target Loss (8%)       5.6
Total Power Available for Workload       62.8

FPGA power consumption can be approximated during Vivado implementation via the report_power command.