The Alveo X3522PV adaptable accelerator card™ supports two UltraScale+™ ™ FPGA configuration modes:
- Quad SPI flash memory
- JTAG (through ADK2 debug connector)
The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 master SPI mode with pull-up/down resistors.
At power up, the FPGA is configured by the Quad SPI NOR flash device using the
master serial configuration mode. Refer to the design constraints (XDC) file for
recommended configuration parameters specified via the various BITSTREAM.CONFIG constraints.
If the JTAG cable is plugged in, QSPI configuration might not occur. JTAG mode is always available independent of the mode pin settings.
For complete details on configuring the FPGA, see the UltraScale Architecture Configuration User Guide (UG570).
| Configuration Mode | M[2:0] | Bus Width | CCLK Direction |
|---|---|---|---|
| Master SPI | 001 | x1, x2, x4 | FPGA output |
| JTAG | Not applicable – JTAG overrides | x1 | Not applicable |