- AArch64 and AArch32 mode
- Support for Cortex-A53 and Cortex-A72 processors
- Execution at Secure Monitor Level EL3 for AArch64 and System mode for AArch32
- AArch64 BSP supports EL1 Non-secure execution on hypervisor
- Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
- Generic counter accessibility
- gcc compiler support
- Floating point support
- Xen PV console support for Cortex A53 EL1 NS domU guests