• Read and write XADC registers
• Serial data transfers to/from XADC
• Buffered read-write data operations
• 15-word by 32-bit command FIFO
• 15-word by 32-bit
• Read Data FIFO
• Programmable FIFO-level interrupts
• Programmable alarm interrupts
• Configured interface operations (using devcfg registers)
• DRP Parallel Interface
• Highest interface bandwidth
• 6-bit sample data