This example does some writes to the hardware to do some sanity checks.
Expected Output
RFdc Read and Write Example Test
DAC00 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC00 Output Current is 32025mA
ADC00 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
ADC00: Link Coupling Mode is 1
DAC01 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC01 Output Current is 32025mA
ADC01 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
ADC01: Link Coupling Mode is 1
DAC02 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC02 Output Current is 32025mA
DAC03 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC03 Output Current is 32025mA
ADC0 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 OutputDivider is 6 ReferenceClk Divider is 1
DAC0 PLL Configurations:: PLL Enable is 1 Feedback Divider is 32 OutputDivider is 2 ReferenceClk Divider is 1
DAC10 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC10 Output Current is 32025mA
ADC10 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
ADC10: Link Coupling Mode is 1
DAC11 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC11 Output Current is 32025mA
DAC12 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC12 Output Current is 32025mA
DAC13 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
DAC13 Output Current is 32025mA
ADC1 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 OutputDivider is 6 ReferenceClk Divider is 1
DAC1 PLL Configurations:: PLL Enable is 1 Feedback Divider is 32 OutputDivider is 2 ReferenceClk Divider is 1
ADC20 Status
DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlagsAsserted - 0
ADC20: Link Coupling Mode is 1
ADC2 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 OutputDivider is 3 ReferenceClk Divider is 1
=======Default DigitalDataPath Configuration for Tile0======
DAC DigitalDataPath0-> Connected I data = 0
DAC DigitalDataPath0-> Connected Q data = -1
ADC DigitalDataPath0-> Connected I data = 0
ADC DigitalDataPath0-> Connected Q data = -1
DAC DigitalDataPath1-> Connected I data = 1
DAC DigitalDataPath1-> Connected Q data = -1
ADC DigitalDataPath1-> Connected I data = 1
ADC DigitalDataPath1-> Connected Q data = -1
DAC DigitalDataPath2-> Connected I data = 2
DAC DigitalDataPath2-> Connected Q data = -1
ADC DigitalDataPath2-> Connected I data = 2
ADC DigitalDataPath2-> Connected Q data = -1
DAC DigitalDataPath3-> Connected I data = 3
DAC DigitalDataPath3-> Connected Q data = -1
ADC DigitalDataPath3-> Connected I data = 3
ADC DigitalDataPath3-> Connected Q data = -1
ADC0 MB Config is 0
DAC0 MB Config is 0
============================================
=============ADC0-4G SB Configuration R2C==========
ADC DigitalDataPath0-> Connected I data = 0
ADC DigitalDataPath0-> Connected Q data = -1
ADC DigitalDataPath1-> Connected I data = 1
ADC DigitalDataPath1-> Connected Q data = -1
ADC DigitalDataPath2-> Connected I data = 2
ADC DigitalDataPath2-> Connected Q data = -1
ADC DigitalDataPath3-> Connected I data = 3
ADC DigitalDataPath3-> Connected Q data = -1
ADC0 MB Config is 0
================================================
=============ADC0,1-4G MB Configuration R2C==========
ADC DigitalDataPath0-> Connected I data = 0
ADC DigitalDataPath0-> Connected Q data = -1
ADC DigitalDataPath1-> Connected I data = 0
ADC DigitalDataPath1-> Connected Q data = -1
ADC DigitalDataPath2-> Connected I data = 2
ADC DigitalDataPath2-> Connected Q data = -1
ADC DigitalDataPath3-> Connected I data = 3
ADC DigitalDataPath3-> Connected Q data = -1
ADC0 MB Config is 1
================================================
=============ADC0,1-4G MB Configuration C2C==========
ADC DigitalDataPath0-> Connected I data = 0
ADC DigitalDataPath0-> Connected Q data = 1
ADC DigitalDataPath1-> Connected I data = 0
ADC DigitalDataPath1-> Connected Q data = 1
ADC DigitalDataPath2-> Connected I data = 2
ADC DigitalDataPath2-> Connected Q data = -1
ADC DigitalDataPath3-> Connected I data = 3
ADC DigitalDataPath3-> Connected Q data = -1
ADC0 MB Config is 1
================================================
=============ADC0,1-4G SB Configuration R2C==========
ADC DigitalDataPath0-> Connected I data = 0
ADC DigitalDataPath0-> Connected Q data = -1
ADC DigitalDataPath1-> Connected I data = 1
ADC DigitalDataPath1-> Connected Q data = -1
ADC DigitalDataPath2-> Connected I data = 2
ADC DigitalDataPath2-> Connected Q data = -1
ADC DigitalDataPath3-> Connected I data = 3
ADC DigitalDataPath3-> Connected Q data = -1
ADC0 MB Config is 0
================================================
=============DAC0 SB Configuration C2R==========
DAC DigitalDataPath0-> Connected I data = 0
DAC DigitalDataPath0-> Connected Q data = -1
DAC DigitalDataPath1-> Connected I data = 1
DAC DigitalDataPath1-> Connected Q data = -1
DAC DigitalDataPath2-> Connected I data = 2
DAC DigitalDataPath2-> Connected Q data = -1
DAC DigitalDataPath3-> Connected I data = 3
DAC DigitalDataPath3-> Connected Q data = -1
DAC0 MB Config is 0
============================================
DAC2,3 MB Config is 2
DAC 4X MB Config is 4
DAC0,1 MB Config is 3
DAC2,3 MB Config is 3
DAC0, 1 SB Config is 2
DAC2, 3 SB Config is 0
Successfully ran Read and Write Example