Test Procedure

Baremetal Drivers and Libraries

Release Date
2023-07-07
@endcode Script will perform following operations 1. Create workspace 2. Create HW project 3. Create BSP 4. Create Application Project 5. Build BSP and Application Project After the process is complete required files will be available in @verbatim bit file -> vpss_example.sdk/vpss_example_hw_platform folder elf file -> vpss_example.sdk/vpss_example_design/{Debug/Release} folder @endverbatim When executed on the board the example application will determine the video processing subsystem topology and set the input and output stream configuration accordingly. Test pattern generator IP is used to generate the input stream. Video Lock Monitor IP will then monitor the output of the subsystem (to vidout) to determine if lock is achieved and present the status (Pass/Fail) on the terminal. @note Serial terminal baud rate should be set to 115200

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END-SSR-BODY END-FRAGMENT dashboard-spa-container-jquery3.html {"serverDuration": 28, "requestCorrelationId": "a3f999a1f142f536"}