The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft Xilinx IP core for use with the Xilinx Vivado Design Suite. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides Scatter Gather (SG) interface with multiple channel support with independent configuration
- AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
- AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512, and 1,024 bits
- Supports up to 16 independent channels
- Supports per Channel Interrupt output
- Supports data realignment engine (DRE) alignment for streaming data width of up to 512 bits
- Supports up to 64 MB transfer per Buffer Descriptor (BD)
- Optional AXI4-Stream Control and Status Streams