2016.3
- None
- None
- Added CCI support in SATA if "dma-coherent" flag is enabled in device-tree node
- Corrected the sequence of AXI bus configuration register programming
- Added Common Clock Framework for SATA
- None
- Corrected suspend/resume logic for SATA
- Added SMMU support for SATA IP
- None
- Merged 4.14 mainline kernel
- None
2018.3 Summary:
- None
2019.1 Summary:
- None
2019.2 Summary:
- None
2020.1 Summary:
-
None
2020.2 Summary:
-
None
2021.1 Summary:
- Update the driver to support xilinx GT phy based on new flow GT driver
- Updated code by using dev_err_probe
Note: This new psgtr configuration is applicable from release Xilinx - 2021.1.
Commits: 07246 c10912021.2 Summary:
-
None
2022.1 Summary:
- None
2022.2 Summary:
-
None
2023.1 Summary:
- None