The 4 datagen blocks are meant to mimic stream sources. They are continuously streaming data and are throttled back by the switch. Below is an image of the stream circuits showing how they generate streaming data.
The binary counters create the identifiable data (incremented or decremented data), while the subset converter creates the tlast pulse to the stream.
All of the data generators are routed to an AXI4 Stream Switch IP to manage the routing of the streams. Below are the options selected. It is important for the switch to arbitrate on TLAST since the MCDMA does not support interleaving of data streams.
Another consideration with using the AXI4-Stream Switch is “Arbitrate on number LOW TVALID cycles” option. In this prototype, the data is constantly streaming in so TVALID will not go low. However, if a custom hardware design does anticipate TVALID to go low, for many cycles, it may need to be buffered prior to entering the switch to prevent arbitration in the middle of a packet.
