Device Tree binding

nwl_pcie: pcie@fd0e0000 {
    #address-cells = <3>;
    #size-cells = <2>;
    compatible = "xlnx,nwl-pcie-2.11";
    #interrupt-cells = <1>;
    msi-controller;
    device_type = "pci";
    interrupt-parent = <&gic>;
    interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
    interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
            <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
    clocks = <&clkc 23>
 
    msi-parent = <&nwl_pcie>;
    reg = <0x0 0xfd0e0000 0x0 0x1000>,
          <0x0 0xfd480000 0x0 0x1000>,
          <0x80 0x00000000 0x0 0x1000000>;
    reg-names = "breg", "pcireg", "cfg";
    ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
          0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 
    pcie_intc: legacy-interrupt-controller {
        interrupt-controller;
        #address-cells = <0>;
        #interrupt-cells = <1>;
    };
 
};