Below device tree mentions the offset and size of the different registers which can be accessed using the Xilinx Secure Configuration driver:
versal_sec_cfg: versal-sec-cfg {
compatible = "xlnx,versal-sec-cfg";
#address-cells = <1>;
#size-cells = <1>;
bbram_zeroize: bbram-zeroize@4 {
reg = <0x04 0x4>;
};
bbram_key: bbram-key@10 {
reg = <0x10 0x20>;
};
bbram_usr: bbram-usr@30 {
reg = <0x30 0x4>;
};
bbram_lock: bbram-lock@48 {
reg = <0x48 0x4>;
};
user_key0: user-key0@110 {
reg = <0x110 0x20>;
};
user_key1: user-key1@130 {
reg = <0x130 0x20>;
};
user_key2: user-key2@150 {
reg = <0x150 0x20>;
};
user_key3: user-key3@170 {
reg = <0x170 0x20>;
};
user_key4: user-key4@190 {
reg = <0x190 0x20>;
};
user_key5: user-key5@1B0 {
reg = <0x1B0 0x20>;
};
user_key6: user-key6@1D0 {
reg = <0x1D0 0x20>;
};
user_key7: user-key7@1F0 {
reg = <0x1F0 0x20>;
};
};
The following table gives the overview of possible addresses for read/write and with the sizes.
|
Register |
Read |
Write |
Size in bytes |
Offset is |
|
BBRAM Zeroize |
NO |
YES |
0x4 |
0x4 |
|
BBRAM Key |
NO |
YES |
0x20 |
0x10 |
|
BBRAM User data |
YES |
YES |
0x4 |
0x30 |
|
BBRAM Lock |
NO |
YES |
0x4 |
0x48 |
|
User Key0 |
NO |
YES |
0x20 |
0x110 |
|
User Key1 |
NO |
YES |
0x20 |
0x130 |
|
User Key2 |
NO |
YES |
0x20 |
0x150 |
|
User Key3 |
NO |
YES |
0x20 |
0x170 |
|
User Key4 |
NO |
YES |
0x20 |
0x190 |
|
User Key5 |
NO |
YES |
0x20 |
0x1B0 |
|
User Key6 |
NO |
YES |
0x20 |
0x1D0 |
|
User Key7 |
NO |
YES |
0x20 |
0x1F0 |
Link to device tree binding file : https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/nvmem/xlnx,versal-sec-cfg.yaml