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Direct mode of memory mapped operation.
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Software triggered IO mode (STIG) up to 8-bytes of data transfers.
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Indirect DMA reads.
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NON-DMA read and write support
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Local SRAM to reduce AHB overhead.
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Supports SDR and DDR protocols.
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Programmable master mode clock frequencies.
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Serial clock with programmable polarity.
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Programmable peripheral selects (chip select).
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Support for Single and Octal instructions.
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Interrupts and polled based operations.