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Single AXI INTC IP supports 32 interrupts, multiple AXI INTC IP's can be cascaded, to support more than 32 interrupt inputs
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Supports chaining with GIC "PL peripheral→ AXI INTC→ GIC→ ARM processor"
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Experimental support to load driver as module (IRQCHIP Xilinx Intc driver module support)
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Enable that feature in the kernel configuration when using the AXI INTC in a PL overlay
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