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Support Low level (Generic) Access
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Support Future Commands
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Supports 3,4,6…N byte addressing
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Supports Command Queuing (Generic FIFO depth is 32)
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Supports 4 or 8-bit interface
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Supports 2 Chip Select Lines
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Supports 4-Bit Bi-Directional I/O signals
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Supports x1/x2/x4 Read/Write
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Supports 44-bit address space on AXI in DMA mode
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Supports byte stripe when two data buses are connected
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Supports single interrupt for QSPI/DMA Interrupt status