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Compliant to industry standard I2C protocol
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Register access through AXI4-Lite interface
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Master or slave operation
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Multi-master operation
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Software selectable acknowledge bit
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Arbitration lost interrupt with automatic mode switching from master to slave
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Calling address identification interrupt with automatic mode switching from master to slave
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START and STOP signal generation and detection
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Repeated START signal generation •
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Acknowledge bit generation and detection
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Bus busy detection •
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Fast-Mode Plus 1 MHz, Fast Mode 400 kHz, or Standard Mode 100 kHz operation
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7-bit or 10-bit addressing • General call enable or disable
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Transmit and receive FIFOs – 16 bytes deep
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Throttling
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General purpose output, 1-bit to 8 bits wide
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Dynamic Start and Stop generation