The Xilinx device tree generator ( https://github.com/Xilinx/device-tree-xlnx ) currently lacks automated support for device tree overlay generation for Partial Reconfiguration / DFX designs. For systems requiring runtime device tree overlay (eg, Linux device driver support) support, hand-crafted device trees can be deployed and loaded. See the "Working with Device Tree Overlay (DTBO)" section below for details on how to load these at runtime.
Occasionally, bare-metal applications relying on the XilFPGA library may produce an error getting the DONE status. See Answer Record 70504 for more details - https://www.xilinx.com/support/answers/70504.html
Few considerations that user should be aware of in programming the PL/FPGA are as follows.
- If the user tries to load the un-aligned bit/bin file the PL configuration takes a longer time when compared with aligned(word-aligned) bit/bin files.
- Using overlay’s we can add a new node or add/update the existing node properties. But it will not allow replacing the existing nodes which is already part of the live tree.
-
If the PL design is having axi-intc IP, the relevant DT node should be the top-node in the overlay.dtsi or pl.dtsi file before its actually being referenced in any other nodes.
- Also, IRQCHIP Xilinx Intc driver module support must be enabled in the kernel configuration.
Example DT node.
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&fpga_full>;
overlay0: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "system.bit.bin";
resets = <&zynqmp_reset 116>;
};
};
fragment@1 {
target = <&amba>;
overlay1: __overlay__ {
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x000>;
};
};
};
fragment@2 {
target = <&amba>;
overlay2: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
axi_intc_1: interrupt-controller@a00d0000 { /* Top node */
#interrupt-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
interrupt-names = "irq";
interrupt-parent = <&axi_intc_0>;
interrupts = <1 2>;
reg = <0x0 0xa00d0000 0x0 0x10000>;
xlnx,kind-of-intr = <0x360>;
xlnx,num-intr-inputs = <0xe>;
};
axi_iic_0: i2c@a0000000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
reg = <0x0 0xa0000000 0x0 0x1000>;
};
axi_iic_1: i2c@a0008000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&axi_intc_1>;
interrupts = <1 2>;
reg = <0x0 0xa0008000 0x0 0x1000>;
};
};
};
};