The Xilinx device tree generator ( https://github.com/Xilinx/device-tree-xlnx ) currently lacks automated support for device tree overlay generation for Partial Reconfiguration / DFX designs. For systems requiring runtime device tree overlay (eg, Linux device driver support) support, hand-crafted device trees can be deployed and loaded. See the "Working with Device Tree Overlay (DTBO)" section below for details on how to load these at runtime. Few considerations that user should be aware of in programming the PL are as follows
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For the Versal platform, it is expected that the base PDI will always be part of BOOT PDI and will be loaded by PLM at boot time. Later from Linux, users can load either the Full/partial PDI from Linux. The term Full bitstream/PDI in Versal implies the whole PL region programming except the configuration that's part of base PDI.
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Using overlays we can add a new node or add/update the existing node properties. But it will not allow replacing the existing nodes which are already part of the live tree.
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If the PL design has axi-intc IP the relevant DT node should be the top-node in the overlay.dtsi or pl.dtsi file
Example DT node:
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&fpga>;
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "system.pdi";
};
};
fragment@1 {
target = <&amba>;
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
axi_intc_1: interrupt-controller@a00d0000 { /* Top node */
#interrupt-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a";
interrupt-controller ;
interrupt-names = "irq";
interrupt-parent = <&axi_intc_0>;
interrupts = <1 2>;
reg = <0x0 0xa00d0000 0x0 0x10000>;
xlnx,kind-of-intr = <0x360>;
xlnx,num-intr-inputs = <0xe>;
};
axi_iic_0: i2c@a0000000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
reg = <0x0 0xa0000000 0x0 0x1000>;
};
axi_iic_1: i2c@a0008000 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk_wiz_0 0>;
compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&axi_intc_1>;
interrupts = <1 2>;
reg = <0x0 0xa0008000 0x0 0x1000>;
};
};
};
};