This is an interrupt asserted by a signal to the GIC. It can be classified in two ways.
1. Private Peripheral Interrupt <or> Shared Peripheral Interrupt
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Private Peripheral Interrupt (PPI)- This is a peripheral interrupt that is specific to a single processor.
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Shared Peripheral Interrupt (SPI) - This is a peripheral interrupt that the Distributor can route to any of a specified combination of processors.
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NOTE: For Zynq UltraScale+ MPSoC Interrupts the GIC - 32 (i.e. PL_PS_Group0 121-32 = 89)
2. Edge-triggered or Level-sensitive
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Edge-triggered - This is an interrupt that is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until it is cleared by the conditions defined by this specification.
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Level-sensitive - This is an interrupt that is asserted whenever the interrupt signal level is active, and deasserted whenever the level is not active.