The system monitor enables you to view the values of PS/PMC and CPM clocks, resets, and related information.
Clock Table
The clock table displays selected PLL, divider, target frequency, and the
actual frequency for PS/PMC and CPM modules in respective tabs. Click the DOWNLOAD button to download the clock frequency
details displayed in the table. The naming convention used for clocking registers
are: <module_name>_<clocking_registers_name>. The Clock Enable field indicates whether the respective
clock is enabled or disabled.
Figure 1. Clock Table
Clock Tree
The clock tree shows clock frequency values and displays all available PLL
clock hierarchy. The default value used for the reference clock is 33.33 MHz. You
can change clock frequencies by editing the Ref Clock. This automatically updates
all respective clock frequencies shown in the GUI, but does not update any clock
frequencies on the board itself. When you update reference clock frequencies on the
board, you need to update the value in the ACAP Cockpit. You will be prompted for
permission to do so. Click Ok to implement
the change.
Figure 2. Clock Tree
Note: The change in clock
value is specific to the tab. For example, if you change the reference clock in
the PS, then only PS clock tree frequencies are calculated based on the new
value.
Click the REFRESH button to read live clock frequencies for all available PLL (APLL, NPLL, PPLL, and RPLL).
Reset Table
The reset table indicates the live values from the board's CRL, CRF, and CRP
module reset registers. If the live value matches the reset value, the live value is
displayed in black, otherwise it is displayed in an amber color. Click the
DOWNLOAD button to download the table's
content.
Figure 3. Reset Table