After the AI Engine kernels, graph, PL kernel, and HLS kernels have been compiled and simulated, you can use
v++ to link them with the platform to generate an
v++ lets you integrate your AI Engine, HLS, and RTL kernels into an existing extensible platform. This step is where the platform chosen is provided by the hardware designer (or you can opt to use one of the many extensible base platforms provided by AMD and have
v++ build the hardware design for you in addition to integrating the AI Engine and PL kernels in the design.
You have a number of kernels at your disposal, but you need to tell the linker how you want to connect them together (from the AI Engine array to PL and vice versa). These connections are described in a configuration file:
system.cfg, shown below.
[connectivity] nk=mm2s:1:mm2s nk=s2mm:1:s2mm sc=mm2s.s:ai_engine_0.DataIn1 sc=ai_engine_0.DataOut1:s2mm.s
||Specifies the number of instantiations of the kernel. For example,
||Specifies the streaming connections to be made between PL/AI Engine or PL/PL. In this case, it should always be an output of a kernel to the input of a kernel.|
v++ command line can get cluttered, and using the
system.cfg file can help contain it.
ai_engine_0 the names are provided in the
graph.h. For the design, as an example, this line:
in = adf::input_plio::create("DataIn1", adf::plio_32_bits,"data/input.txt");
has the name DataIn1 which is the interface name.
You can see the
v++ switches in more detail in the Vitis Unified Software Platform Documentation.
To build the design run the follow command:
v++ -l --platform -t sw_emu $PLATFORM_REPO_PATHS/xilinx_vek280_es1_base_202320_1/xilinx_vek280_es1_base_202320_1.xpfm s2mm.xo mm2s.xo libadf.a --save-temps -g --config system.cfg -o tutorial.xsa
||Same as the previous two steps.|
||This allows you to simplify the v++ command line if it gets too unruly and have items in an
Now you have a generated
.xsa that will be used to execute your design on the platform.