AI Engine to PL to DDR Memory - 2022.2 English

Vitis Tutorials: AI Engine Development

Document ID
XD100
Release Date
2022-12-01
Version
2022.2 English

After the RTP update has been sent, you can start to see output data being written to DDR memory. In this design, the AI Engine is sending data from the S00_AXIS interface and getting it to the s2mm kernel. This kernel is a FIFO written in HLS and is used to write the output to DDR memory.

  1. To view these signals run the following.

    source ../../../../tcl/aie_to_ddr.tcl
    

    You should see something similar to the following.

    AIE to DDR

    As you can see, the transactions in green are slightly ahead of the tan. This means those signals are going first. The data path is the AI Engine kernel, to the interface tile, then to the AIENGINE/M00_AXIS interface. Notice how AIENGINE/M00_AXIS and S2MM/s interfaces are matched, meaning they are connected together. The same applies to the S2MM/m_axi_gmem and the DDR4/S00_AXI interfaces on the noc_ddr4 IP.

    After the data is stored into DDR memory, the host application can then access it.

  2. Expand the CIPS_NOC group. Notice that the last transactions on the cips_noc_0_M00_AXI_tlm and the cips_noc_0_S00_AXI_tlm interfaces as following. This is the host application reading the data that was stored by the s2mm kernel.

    DDR to PS

    Zoom in and you should see the following.

    DDR to PS zoom in

  3. When emulation is finished, close the XSIM GUI, which closes the QEMU and the emulation. Discard the waveform at the pop-up prompt.

  4. Navigate back to the terminal that launched emulation.